View ZADCS1022VIS14T_7568914.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet rev. 2.0 / october 2011 zadcs1082/1042/1022 10-bit, 250ksps, adc family
zadcs1082/1042/1022 10-bit, 250ksps, adc family ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. ns possible due to downward compatibility within the family power t ? zadcs1282 kit or zmdi zadcs10x2 family s1282 device ? adc resoluti on............................ 10 bit ............ 250 ksps 5.25v ax. ply ? ? brief description the zmdi zadcs1082/zadcs1042/zadcs1022 are 10-bit low power analog-to-digital (a/d) converters with up to 250ksps conversion rate. the converter is based on successive- approximation-register architecture. all converters have an 8-channel input multiplexer and a high-bandwidth a track/hold circuit. all analog inputs are software configurable as eight / four/two single ended or four/two/one differential analog input channels as well as for unipolar or bipolar output coding. the zadcs1082/ zadcs1042/ zadcs1022 operate from a single +2.7v to +5.25v supply. the synchronous four wire serial interface connects directly to a microcontroller using one of the standards like spi?, qspi?, and microwire? without external components. the zadcs1082/zadcs1042/zadcs1022 use either the external serial-interface clock or an internally generated clock to perform successive- approximation analog-to-di gital conversions. the internal clock mode can be used to run synchronous conversions on several zmdi adcs in parallel. the ?v? versions zadcs1082v/zadcs1042v/ zadcs1022v are equipped with a high accurate internal 2.5v reference with an additional external 1.5% voltage adjustment range. the device provides a hard-wired shut-down pin (nshdn) and software-selectable power-down modes to automatically shut down the ic at the end of a conversion. accessing the serial interface automatically power s up the zadcs1082/ zadcs1042/zadcs1022. a quick turn-on time allows the device to be shut down between measurements. features ? 10-bit resolution sar adc ? 2/4/8 channel single or 1/2/4 channel diff. inputs ? software configurable uni- or bipolar output code ? spi?/qspi?, microwire? compatible serial interface ? no missing codes ? low power consumption ? internal 2.5v reference (only ?v? version - zadcs1082v/ zadcs1042v/zadcs1022v) ? software programmable power down mode ? single-supply operation +2.5v to +5.25v b enefits ? scalable system solutio upward/ ( 8, 10, 12 bit resolution, 2, 4, 8 channels) ? accurate measurements ? long battery life cycles due to low c onsumption ? synchronous sampling with several zadcs parts in parallel a vailable suppor - evaluation kit f b ased on zadc - standalone and pc based operation modus - usb 2.0 (1.1) compatible - user interface for pc operated modus l. and fft analyzer - graphical oscilloscope app p hysical characteristics ? conversion ra te............... ? power supply rate ....................... 2.7v to ? inl............................................... 0.4 lsb m ? dnl ............................................. 0.4 lsb max. ? sinad ......................................... >61 db ? standby (idle) current.................. <0.5 a ? current consumption @ 200 ksps, 3v sup - with internal reference .............. < 1.2 ma - without internal reference ......... < 0.9 ma 85c temperature range ..................... -25c to + 14 / 16 / 20-pin ssop package
zadcs1082/1042/1022 10-bit, 250ksps, adc family ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. typical applications ? embedded control & real time appl. ? industrial control & process control applications ? motion control applications ? three phase motor control ? power generation (solar, windmills, etc.) ? data acquisition ? portable data logging ? battery-powered systems ? automotive zadcs1082 block diagram x 2.00 8-channel analog input multiplexer sar dac with inherent t&h + - in - in + comparator internal 3.2 mhz oscillator +1.25v reference serial interface and control state machine ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com refadj vref ncs sclk din dout sstrb nshdn vdd dgnd agnd available in zadcs1082v / zadcs1042v / zadcs1022v ordering information order code resolution [bit] channels [number] sample rate [ksps] temperature range [c] internal vref inl dnl pins [number] package [type] packing zadcs1082 vis20t 10 8 250 -25c to +85c ? 0,4 lsb 0,4 lsb 20 ssop tube zadcs1082 is20t 10 8 250 -25c to +85c -- 0,4 lsb 0,4 lsb 20 ssop tube zadcs1042 vis16t 10 4 250 -25c to +85c ? 0,4 lsb 0,4 lsb 16 ssop tube zadcs1042 is16t 10 4 250 -25c to +85c -- 0,4 lsb 0,4 lsb 16 ssop tube zadcs1022 vis14t 10 2 250 -25c to +85c ? 0,4 lsb 0,4 lsb 14 ssop tube zadcs1022 is14t 10 2 250 -25c to +85c -- 0,4 lsb 0,4 lsb 14 ssop tube sales and further information www.zmdi.com adc@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 8413 excelsior drive suite 200 madison, wi 53717 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan phone +49 (0)351.8822.7232 fax +49 (0)351.8822.87232 phone +1 (608) 829-1987 fax +1 (631) 549-2882 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886 2 2377 8189 fax +886 2 2377 8199 disclaimer : this information applies to a product under development. its characteristics and specifications are preliminary and subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. t he information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this te chnical data. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third par ty hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contra ct, warranty, tort (including negligence), strict liability, or otherwise.
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 4 of 26 contents 1 ..............................................................................................................................7 general device specification 1.1. ...............................................................................................7 absolute maximum ratings (non operating) 1.2. ..............................................................................8 package pin assignment zadcs1082 / zadcs1082v 1.3. ..............................................................................9 package pin assignment zadcs1042 / zadcs1042v 1.4. ............................................................................10 package pin assignment zadcs1022 / zadcs1022v 1.5. ............................................................................................................................11 electrical characteristics 1.5.1. .............................................................................................................................11 general parameters 1.5.2. ..........................................12 specific parameters of zadcs10x2v versi ons (with internal reference) 1.5.3. ..............................13 specific parameters of basic zadcs10x 2 versio ns (without internal reference) 1.5.4. .........................................................................................................................13 digital pin parameters 1.6. ...............................................................................................................14 typical operating characteristics 2 ............................................................................................................................... ........... 15 detailed description 2.1. ............................................................................................................................... ....... 15 general operation 2.2. ............................................................................................................................... ................. 16 analog input 2.3. ....................................................................................................................18 internal & external reference 2.4. ............................................................................................................................... ............ 18 digital interface 2.5. ............................................................................................................................... ........ 22 power dissipation 3 ............................................................................................................................... ................................. 24 layout 4 ............................................................................................................................... ............... 25 package drawing
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 5 of 26 list of figures figure 1 package pin assignment for zadcs1082 & zadcs1082v ........................................................................8 figure 2 package pin assignment for zadcs1042 & zadcs1042v ........................................................................9 figure 3 package pin assignment for zadcs1022 & zadcs1022v ......................................................................10 figure 4: basic application schematic for zadcs1082v .........................................................................................15 figure 5: basic application schematic for zadcs1082 ............................................................................................15 figure 6: input voltage range in unipolar mode ........................................................................................................16 figure 7: input voltage range for bipolar mode ........................................................................................................16 figure 8: block diagram of input multiplexer ............................................................................................................17 figure 9: equivalent input circuit during sampling ....................................................................................................17 figure 10: reference adjust circuit ..........................................................................................................................18 figure 11: 24-clock external clock mode timing (f 3.3mhz) sclk .........................................................................19 figure 12: internal clock mode timing with interleaved control byte transmission ................................................19 figure 13: 16-clock external clock mode conversion .............................................................................................20 figure 14: 13-clock external clock mode conversion .............................................................................................20 figure 15 detailed timing diagram ..........................................................................................................................21 figure 16: unipolar transfer function ......................................................................................................................22 figure 17: bipolar transfer function ........................................................................................................................22 figure 18: supply current versus sampling rate ....................................................................................................24 figure 19: optimal power-supply grounding system ..............................................................................................24 figure 20: package outline dimensions ..................................................................................................................25
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 6 of 26 list of tables table 1: absolute maximum ratings ..........................................................................................................................7 table 2: pin list zadcs1082 / zadcs1082v ............................................................................................................8 table 3: pin list zadcs1042 / zadcs1042v ............................................................................................................9 table 4: pin list zadcs1022 / zadcs1022v ..........................................................................................................10 table 5: channel selection in single ended mode ...................................................................................................15 table 6: channel selection in differential mode .......................................................................................................15 table 7 control byte format ............................................................................................................................... ..... 19 table 8: timing characterisitics (vdd = +2.7v to + 5.25v; ? = ? ? ? ) op opmin opmax ...............................................21 table 9: package dimensions for zadc1082 devices (mm) ...................................................................................25 table 10: package dimensions for zadc1042 devices (mm) .................................................................................25 table 11: package dimensions for zadc1022 devices (mm) .................................................................................25
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 7 of 26 1 general device specification 1.1. absolute maximum ratings (non operating) symbol parameter min max unit note v dd-gnd vdd to agnd, dgnd -0.3 6 v v agnd-dgnd agnd to dgnd -0.3 0.3 v ch0 ? ch7, com to agnd, dgnd -0.3 vdd+0.3 v vref, vrefadj to agnd -0.3 vdd+0.3 v digital inputs to dgnd -0.3 6 v digital outputs to dgnd -0.3 vdd+0.3 v digital output sink current 25 ma i in input current into any pin except supply pins (latch-up) -100 100 ma v hbm electrostatic discharge ? human body model (hbm) 2000 v 1 ? jct maximum junction temperature +150 c ? op operating temperatur e range -25 +85 ? stg storage temperature -65 +150 c ? lead lead temperature 100%sn jedec-j-std-20c 260 c h humidity non-condensing 2 p tot total power dissipation 250 mw thermal resistance of package r thj ssop20 / 5.3mm 100 k/w table 1: absolute maximum ratings 1 hbm: c = 100pf charged to v hbm with resistor r = 1.5k ? in series, valid for all pins 2 level 4 according to jedec-020a is guaranteed
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 8 of 26 1.2. package pin assignment zadcs1082 / zadcs1082v package pin numb er name direction type description 1 ncs in cmos digital active low chip select 2 din in cmos digital serial data input 3 dgnd supply digital ground 4 agnd supply analog ground 5 vref i/o analog reference buffer ou tput / external reference input 6 com in analog ground reference for analog inputs in single ended mode 7 ch0 in analog analog input channel 0 8 ch1 in analog analog input channel 1 9 ch4 in analog analog input channel 4 10 ch5 in analog analog input channel 5 11 ch7 in analog analog input channel 7 12 ch6 in analog analog input channel 6 13 ch3 in analog analog input channel 3 14 ch2 in analog analog input channel 2 15 refadj i/o analog input to reference buffer amplifier 16 vdd supply positive supply 17 nshdn in cmos digital active low shutdown 18 dout out cmos digital serial data output 19 sstrb out cmos digital serial strobe output 20 sclk in cmos digital serial clock input table 2: pin list zadcs1082 / zadcs1082v figure 1 pac kage pin assignment for zadcs1082 & zadcs1082v ncs sclk sstrb din zadcs 1082 / zadcs 1082v dou t dgnd nshdn agnd vdd vref refadj on zadcs1082 v , com no connect on zadcs1082 ch2 ch0 ch3 ch1 ch6 ch4 ch7 ch5
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 9 of 26 1.3. package pin assignment zadcs1042 / zadcs1042v package pin number name direction type description 1 ncs in cmos digital active low chip select 2 din in cmos digital serial data input 3 dgnd supply digital ground 4 agnd supply analog ground 5 vref i/o analog reference buffer ou tput / external reference input 6 com in analog ground reference for analog inputs in single ended mode 7 ch0 in analog analog input channel 0 8 ch1 in analog analog input channel 1 9 ch3 in analog analog input channel 3 10 ch2 in analog analog input channel 2 11 refadj i/o analog input to reference buffer amplifier 12 vdd supply positive supply 13 nshdn in cmos digital active low shutdown 14 dout out cmos digital serial data output 15 sstrb out cmos digital serial strobe output 16 sclk in cmos digital serial clock input table 3: pin list zadcs1042 / zadcs1042v figure 2 pac kage pin assignment for zadcs1042 & zadcs1042v ncs sclk zadcs 1042 / zadcs 1042v sstrb din dou t dgnd nshdn agnd vdd vref refadj on zadcs1042 v , com no connect on zadcs1042 ch2 ch0 ch3 ch1
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 10 of 26 1.4. package pin assignment zadcs1022 / zadcs1022v package pin numb er name direction type description 1 ncs in cmos digital active low chip select 2 din in cmos digital serial data input 3 dgnd supply digital ground 4 agnd supply analog ground 5 vref i/o analog reference buffer ou tput / external reference input 6 com in analog ground reference for analog inputs in single ended mode 7 ch0 in analog analog input channel 0 8 ch1 in analog analog input channel 1 9 refadj i/o analog input to reference buffer amplifier 10 vdd supply positive supply 11 nshdn in cmos digital active low shutdown 12 dout out cmos digital serial data output 13 sstrb out cmos digital serial strobe output 14 sclk in cmos digital serial clock input table 4: pin list zadcs1022 / zadcs1022v figure 3 pac kage pin assignment for zadcs1022 & zadcs1022v ncs sclk sstrb din zadcs 1022 zadcs 1022v dou t dgnd nshdn agnd vdd vref refadj on zadcs1022 v , com no connect on zadcs1022 ch1 ch0
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 11 of 26 1.5. electrical characteristics 1.5.1. general parameters (vdd = +2.7v to + 5.25v; f sclk = 3.3mhz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); v ref = 2.500v applied to vref pin; ? op = ? opmin ? ? opmax ) parameter symbol conditions min typ max unit dc accuracy resolution 10 bits relative a ccuracy inl zadcs1082 / zadcs1082 v zadcs1042 / zadcs1042 v zadcs1022 / zadcs1022 v ? 0.4 lsb no missing codes nmc 10 bits differential nonlinearity dnl zadcs1082 / zadcs1082 v zadcs1042 / zadcs1042 v zadcs1022 / zadcs1022 v ? 0.4 lsb offset error ? 0.5 ? 2.0 lsb gain error ? 0.5 ? 2.0 lsb gain temperature coefficient ? 0.25 ppm/c dynamic specifications (10khz sine-wave input, 0v to 2.500vpp, 250ksps, 3.3mhz external clock) signal-to-noise + distortion ratio sinad 61 db total harmonic distortion thd up to the 5 th harmonic -72 db spurious-free dynamic range sfdr 74 db small-signal bandwidth -3db roll off 3.8 mhz conversion rate sampling time (= track/hold acquisition time) t acq ext. clock = 3.3mhz, 2.5 clocks/ acquisition 0.758 s ext. clock = 3.3mhz, 10 clocks/ conversion 3.03 s conversion time t conv int. clock = 3.3mhz +/- 12% tolerance 2.75 3.50 s aperture delay 30 ns aperture jitter < 50 ps external clock frequency 0.1 3.3 mhz internal clock frequency 2.81 3.3 3.58 mhz analog inputs unipolar, com = 0v 0 to vref input voltage range, single- ended and differential bipolar, com = vref/2 ? vref / 2 v input capacitance 16 pf
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 12 of 26 1.5.2. specific parameters of zadcs10x2v ve rsi ons (with internal reference) (vdd = +2.7v to + 5.25v; f sclk = 3.3mhz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); ? op = ? opmin ? ? opmax ) parameter symbol conditions min typ max unit internal reference at vref vref output voltage t a = + 25c 2.480 2.500 2.520 v vref short-circuit current 30 ma vref temperature coefficient 30 50 ppm/c load regulation 0 to 0.2ma output load 0.35 mv capacitive bypass at vref 4.7 f capacitive bypass at refadj 0.047 f refadj adjustment range ? 1.5 % external reference at vref (internal buffer disabled by v(refadj) = vdd ) vref input voltage range 1.0 vdd + 50mv v vref input current vref = 2.5v 180 215 a vref input resistance 11.5 14 k? shutdown vref input current 0.1 a refadj buffer disable threshold vdd- 0.5 v external reference at vref_adj reference buffer gain 2.00 vref_adj input current 80 a full power down vrefadj input current full power-down mode 0.1 a power requirements positive supply voltage vdd 2.7 5.25 v operating mode ext. vref 0.85 1.0 ma operating mode int. vref 1.3 1.4 ma fast power-down 250 300 positive supply current zadcs1082 vi zadcs1042 vi zadcs1022 vi idd vdd=3.6v full power-down 0.5 4.0 a operating mode ext. vref 1.00 1.3 ma operating mode int. vref 1.40 1.6 ma fast power-down 250 300 positive supply current zadcs1082 vi zadcs1042 vi zadcs1022 vi idd vdd=5.2v full power-down 0.5 4.0 a
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 13 of 26 1.5.3. specific parameters of basic zadcs10x2 versio ns (without internal reference) (vdd = +2.7v to + 5.25v; f sclk = 3.3mhz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); ? op = ? opmin ? ? opmax ) parameter symbol conditions min typ max unit external reference at vref vref input voltage range 1.0 vdd + 50mv v vref input current vref = 2.5v 180 215 a vref input resistance 11.5 14 k? shutdown vref input current 0.1 a capacitive bypass at vref 4.7 f power requirements positive supply voltage vdd 2.7 5.25 v operating mode 0.85 1.0 positive supply current zadcs1082 i zadcs1042 i zadcs1022 i idd vdd = 3.6v full power-down 0.5 4.0 a operating mode 1.00 1.3 positive supply current zadcs1082 i zadcs1042 i zadcs1022 i idd vdd = 5.25v full power-down 0.5 4.0 a 1.5.4. digital pin parameters (vdd = +2.7v to + 5.25v; f sclk = 3.3mhz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); ? op = ? opmin ? ? opmax ) parameter symbol conditions min typ max unit digital inputs (din, sclk, cs, nshdn) vdd = 2.7v 1.9 v logic high level v ih vdd = 5.25v 3.3 v vdd = 2.7v 0.7 v logic low level v il vdd = 5.25v 1.4 v hysteresis v hyst 0.7 v input leakage i in vin = 0v or vdd 0.1 1.0 a input capacitance c in 5 pf digital outptus (dout, sstrb) vdd = 2.7v 3.5 8.5 ma output high current i oh v oh = vdd ? 0.5v vdd = 5.25v 5.5 10.8 ma vdd = 2.7v 4 11.5 ma output low voltage i ol v ol = 0.4v vdd = 5.25v 6.4 15.3 ma three-state leakage current i leak ncs = vdd 0.1 1.0 a three-state output capacitance c out ncs = vdd 5 pf
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 14 of 26 1.6. typical operating characteristics integral nonlinearity vs. code -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 128 256 384 512 640 768 896 1024 code inl (lsb) differential nonlinearity vs. code -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 128 256 384 512 640 768 896 1024 code dnl (lsb) idd vs. vdd 0 150 300 450 600 750 900 1050 1200 1350 1500 2.73.44.14.8 vdd (v) idd (a) 5 . 5 iddstatic vs. temperature zadcs12x2v, internal reference active, at vdd = 3.3v 500 550 600 650 700 -40 -20 0 20 40 60 80 100 temperatur (c) idd (a) iddactive (converting) vs. temperature zadcs12x2v, internal reference active, at vdd = 3.3v 900 950 1000 1050 -40-20 0 20406080100 temperatur (c) idd (a) v ref vs. temperature 2.498 2.499 2.500 2.501 -25 0 25 50 75 temperature (c) reference voltage (v) iddactive (converting) iddstatic external v internal v ref ref
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 15 of 26 2 detailed description 2.1. general operation the zadcs 10x2 family is a set of classic successive approximation register (sar) type converters. the architecture is based on a capacitive charge redist ribution dac merged with a resistor string dac building a hybrid converter with excellent monotonicity and dnl properties. the sample & hold function is inherent to the cap acitive dac. this avoids additional active com ponents in the signal path t hat could distort the input signal or introduce errors. all devices in the zadcs10x2 family build on the same converter core and differ only in the number of input channels and the availability of an internal reference voltage generator. the zadcs10x2 v versions are equipped with a highly accurate internal 1.25v bandgap re ference which is available at the vrefadj pin. the bandgap voltage is further amplified by an internal buffer am plifier to 2.50v that is available at pin vref. all other versions come without the internal reference and the internal buffer amplifier. they require an external reference supplied at vref, with the benefit of considerably lower power consumption. a basic application schematic for zadc1082 v is shown in figure 4 , for zadcs1082 in figure 5 . zadcs1 082 v can also be operated with an external reference, if vrefadj is tied to vdd. figure 4: basic applicatio n schematic for zadcs1082v figure 5: basic applicatio n schematic for zadcs1082 a2 a1 a0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 0 0 0 in+ in- 1 0 0 in+ in- 0 0 1 in+ in- 1 0 1 in+ in- 0 1 0 in+ in- 1 1 0 in+ in- 0 1 1 in+ in- 1 1 1 in+ in- table 5: channel selection in single ended mode a2 a1 a0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 0 0 0 in+ in- 0 0 1 in+ in- 0 1 0 in+ in- 0 1 1 in+ in- 1 0 0 in- in+ 1 0 1 in- in+ 1 1 0 in- in+ 1 1 1 in- in+ table 6: channel selection in differential mode single-ended or differential analog inputs, 0v ? +2.5v ncs 1 din 2 dgnd 3 a gnd 4 v ref 5 com 6 ch0 7 ch1 8 ch4 9 ch5 10 sclk 20 sstrb 19 dout 18 nshdn 17 vdd 16 v refadj 15 ch2 14 ch3 13 ch6 12 ch7 11 zadcs1082v 47nf 4.7f 0.1f 10f sck i/o mosi miso c +2.7v to 5.25v single-ended or differential analog inputs, 0v ? +v ref ncs 1 din 2 dgnd 3 a gnd 4 v ref 5 com 6 ch0 7 ch1 8 ch4 9 ch5 10 sclk 20 sstrb 19 dout 18 nshdn 17 vdd 16 n.c. 15 ch2 14 ch3 13 ch6 12 ch7 11 zadcs1082 4.7f 0.1f c mi so mosi sck i/o +2.7v to 5.25v 10f
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 16 of 26 2.2. analog input the a nalog input to the converter is fully differential. both converter input signals in + and in ? (see functional block diagram at front page) get sampled during the ac quisition period enabling the converter to be used in fully differential applications where both signals can vary over time. the zadcs10x2 family converters do not require that the negative input signal be kept constant within 0.5lsb during the entire conversion as is commonly required by converters featuring pseudo differential operation only. the input signals can be applied single ended, referenced to the com pin, or differential, using pairs of the input channels. the desired configurat ion is selectable for every conversion via the control-byte received on din pin of the digital interface (see further description below) a block diagram of the inpu t multiplexer is shown in figure 8 . table 5 and table 6 show the relationship of the control-byte bits a2, a1, a0 and sgl/dif to the confi guration of the analog multiplexer. the entire table applies only to zadcs1082 devices. for zadcs1042 devic es bit a1 is don?t care, for zadcs1022 devices a1 and a0 are don?t care. both input signals in + and in ? are generally allowed to swing between ?0.2v and vdd+0.2v. however, depending on the selected conversion mode ? uniploar or bi polar ? certain input voltage relations can limit the output code range of the converter. in unipolar mode the voltage at in + must exceed the voltage at in ? to obtain codes unequal to 0x00. the entire 8 bit transfer characteristic is then covered by in + if in + ranges from in ? to (in ? +vref). any voltage on in + >(in ? +vref) results in code 0xff. code 0xff is not reached, if (in ? +vref) > vdd + 0.2v because the input voltage is clamped at vdd + 0.2v by esd protection devices. figure 6: input voltage range in unipolar mode figure 7: input voltage range for bipolar mode v v in+ cm the voltage at in ? can range from -0.2v ? ? v ref without limiting the code r ange, assuming the fore mentioned vdd condition is true. see also figure 6 for input voltage ranges in unipolar conversion mode. 0v 1.5*v ref v ref v in- v dd -v ref code range 0xff 0x00 0.5*v ref 0v v ref ? v range v cm ? v ref -v /2 0v +v /2 v ref ref diff
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 17 of 26 in bipola r mode, in + can range from (in ? - vref/2) to (in ? +vref/2) keeping the converter out of code saturation. for instance, if in ? is set to a constant dc voltage of vref/2, then in + can vary from 0v to v ref to cover the entire code range. lower or higher voltages of in + keep the output code at the minimum or maximum code value. figure 7 shows the input voltage ranges in bipolar mode when in ? is set to a constant dc voltage. as explained before, converters out of the zadcs10x2 family can also be used to convert fully differential input signals that change around a common mode input voltage. the bipolar mode is best used for such purposes since it allows the input signals to be positive or negative in relation to each other. the common mode level of a differential input signal is calculated v cm = (v(in + )+ v(in ? )) / 2. to avoid code clipping or over steering of the converter, the common mode level can change from ? v ref ? ? v ref . within this range the peak to peak amplitude of the differential input signal can be v ref /2. the average input current on the analog inputs depends on the conversion rate. the signal source must be capable of charging the internal sampling capacitors (typically 16pf on each input of the converter: in + and in ? ) within the acquisition time t acq to the required accuracy. the equivalent input circuit in sampling mode is shown in figure 9 . the follo wing equation provides a rough hand calculation for a source impedance r s that is required to settle out a dc input signal referenced to agnd with 8 bit accuracy in a given acquisition time sw in acq s r c7 t r ? ? ? for example, if f sclk = 3.3mhz, the acquisition time is t acq = 758ns. thus the output impedance of the signal source r s must be less than 2.41k ? k ? 3 20pf7 758ns r s ?? ? ? if the output impedance of the source is higher than the calculated maximum r s the acquisition time must be extended by reducing f sclk to ensure 8 bit accuracy. another option is to add a capacitor of > 20nf to the individual input. although this limits the bandwidth of the input signal because an rc low pass filter is build together with the source impedance, it may be figure 8: block diagram of input multiplexer sho wn configuration figure 9: equivalent input circuit during sampling ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 a2 ? a0 = 0x 000 in+ converter in- com sgl/dif = high see table 5 & t able 6 for coding schemes r sw c hold+ 16pf c in 4pf r sw ch0 a gnd c hold- 16pf c in 4pf a gnd in + in - ch1 ch2 ch3 ch4 ch5 ch6 ch7 com channel multiplexer 3k v dc 3k
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 18 of 26 useful for certain applications. the small-signal bandwidth of the input tracking circuitry is 3.8mhz. hence it is possi ble to digitize high-speed transient events and periodic signals with frequencies exceeding the adc?s sampling rate. this allows the application of certain under-sampling techniques like down conversion of modulated high frequency signals. be aware that under-sampling techniques still require a band width limitation of the input signal to less than the nyquist frequency of the converter to avoid aliasing e ffects. also, the output impedance of the input source must be very low to achieve the mentioned sm all signal bandwidth in the overall system. 2.3. internal & external reference zadcs1 0x2 v family members are equipped with a highly accu rate internal 2.5v reference voltage source. the voltage is generated from a trimmed 1.25v bandgap with an internal buffer that is set to a gain of 2.00. the bandgap voltage is supplied at vr efadj with an output impedance of 20k ? . an external capacitor of 47nf at vrefadj is useful to further decrease noise on the internal reference. the vrefadj pin also provides an opportunity to exte rnally adjust the bandgap vo ltage in a limited range (see figure 10 ) as well as the possibility to overdrive the inte rn al bandgap with an external 1.25v reference. the internal bandgap reference and the vref buffer can be shut down completely by setting vrefadj to vdd. this reduces power co nsumption of the zadcs10x2 v devices and allows the supply of an external reference at vref. basic zadcs10x2 devices do not contain the internal bandgap or the vref buffer. an external reference must be supplied all the time at vref. the valu e of the reference voltage at vref sets the input range of the converter and the analog voltage weight of each digital code. the size of the lsb (least significant bit) is equal to the value of vref (reference to agnd) divided by 1024. for example at a reference voltage of 2.500v, the voltage level of a lsb is equal to 9.766mv. the average current consumption at vref depends on the value of vref and the sampling frequency. two effects contribute to the current at vref, a resistive connection from vref to agnd and charge currents that result from the switching and recharging of the capacit or array (cdac) during sampling and conversion. for an external reference of 2.5v the input current at vref is approximately 100a. 2.4. digital interface all device s out of the zadcs10x2 family are controlled by a 4-wire serial interface that is compatible to spi?, qspi? and microwire? devices without external logi c. any conversion is started by sending a control byte into din while ncs is low. a typical sequence is shown in figure 11 . the control byte defines the input channel(s), unipolar or bipolar operation and output coding, single-ended or differential input configuration, external or internal conversion clock and the kind of power down that is activated after the completion of a conversion. a detail ed description of the control bits can be obtained from figure 11 . as it can also be seen in figure 11 the acquisition of the input signal occurs at the end of the control byte for 2.5 clo ck cycles. outside this range, the track & hold is in hold mode. the conversion process is star ted, with the falling clock edge (sclk) of the eighth bit in the control byte. it takes twelve clock cycles to complete the conversion and one additional cycle to shift out the last bit of the conversion result. during the remaining seven clock cycles the output is filled with zeros in 24-clock conversion mode. depending on what cloc k mode was selected, either the external spi clock or an internal clock is used to drive the successive approximation. figure 12 shows the timing for internal clock mode. figure 10: reference adjust circuit vdd = +2.7v ? +5.25v z adcs10x2v 510k ? vrefadj 47nf
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 19 of 26 figure 11: 24-clock external clock mode timing (f sclk 3.3mhz) ncs figure 12: internal clock mode timing with interleaved control byte transmission table 7 control byte format bit name description 7 (msb) start the start bit is defined by the first logic ?1? after ncs goes low. 6 5 4 a2 a1 a0 channel select bits. along with sgl/dif these bits control the setting of the input multiplexer. for further details on the decoding see also table 5 and table 6 . 3 uni/bip output code bit. the value of the bit determines conversion mode and output code format. ?1? = unipolar - straight binary coding ?0? = bipolar - two?s complement coding 2 sgl/dif single-ended / differential select bit. along with the channel select bits a2 .. a0 this bit controls the setting of the input multiplexer ?1? = single ended - all channels ch0 ? ch7 measured referenced to com ?0? = differential - the voltage between two channels is measured 1 0 (lsb) pd1 pd0 power down and clock mode select bits pd1 pd0 mode 0 0 full power-down 0 1 fast power-down 1 0 internal clock mode 1 1 external clock mode s a2 a1 a0 uni/ bip sgl/ dif pd1 pd0 b9 b8 b7 b0 zero filled acquire idle conversion ( msb ) ( lsb ) 1 8 ( start ) ncs sclk din sstrb dout b3 b2 b1 b6 b5 b4 18 18 s a2 a1 a0 uni/ bip sgl/ dif pd1 pd0 acquire result output t conv s a2 a1 a0 uni/ bip sgl/ dif pd1 pd0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 zero filled t acq acquire idle conversion idle ( msb ) ( lsb ) 1 8 18 sclk 18 din ( start ) sst rb dout
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 20 of 26 figure 13: 16-clock external clock mode conversion dout sstrb 8 s a2 a1 a0 uni/ bip sgl/ dif pd1 pd0 ( msb ) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 zero filled idle ( lsb ) 1 8 uni/ bip sgl/ dif pd1 pd0 b9 b8 1 acquire a0 a1 a2 s acquire idl e conversion 1 ( start ) ncs din sclk 8 1 figure 14: 13-clock external clock mode conversion sclk ncs s a2 a1 a0 uni/ bip sgl/ dif pd1 pd0 dout sstrb din b9 b8 b7 b6 b5 b4 b3 b1 b0 zero filled ( start ) acquire idl e conversion ( msb ) ( lsb ) 1 8 1 13 a2 a1 a0 uni/ bip sgl/ dif pd1 pd0 acquire b9 b8 13 1 b7 b6 b5 b4 b3 b2 s a2 a0 a1 conversion b2 s internal clock mode in internal clock mode, the conversion starts at t he falling clock edge of the eighth control bit just as in external clock mode. however, there are no further clock pulses required at sclk to complete the conversion. the conversion clock is generated by an internal oscillator that runs at appro ximately 3.3mhz. while the conversion is running, the sstrb signal is dr iven low. as soon as the conversion is complete, sstrb is switched to high, signalling that the conversion result can be re ad out on the serial interface. to shorten cycle times zadcs10x2 family devices allo w interleaving of the read out process with the transmission of a new control byte. thus it is possib le to read the conversion result and to start a new conversion with just two consecutive by te transfers, instead of thee bytes that would have to be send without the interleaving function. while the ic is performing a conversion in internal clock mode, the chip select signal (ncs) may be tied high allowing other devices to communicate on the bus. the output driver at dout is switched into a high impedance state while ncs is high. the conversion time t conv may vary in the specified limits depending on the actual vdd and temperature values. 16-clocks per conversion interleaving of the data read out process and transmis sion of a new control byte is also supported for external clock mode operation. figure 13 shows the transmission timing for conversion runs using 16 clock cy cles per run. 13-clocks per conversion zadcs10x2 family devices do also support a 13 clock cycle conversion mode (see figure 14 ). this is the fastest conve rsion mode possible. in fact, the specified converter sampling rate of 250ksps will be reached in this mode, provided the clock frequency is set to 3.3mhz . usually micro controllers do not support this kind of 13 bit serial communication transfers. however, specif ically designed digital state machines implemented in
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 21 of 26 field prog rammable gate arrays (fpga) or application specific integrated circuits (asic) may use this operation mode. digital timing in general the clock frequency at sclk may vary from 0. 1mhz to 3.3mhz. considering all telegram pauses or other interruptions of a continuous clock at sclk, each conversion must be completed within 1.2ms from the falling clock edge of the eighth bit in the control by te. otherwise the signal that was captured during sample/hold may drop to noticeable affect the conversion result. further detailed timing information on the digital interface is provided in table 8 and figure 15 . parameter symbol conditions min typ max unit sclk periode t sclk 303.0 ns sclk pulse width high t sclkhigh 151.5 ns sclk pulse width low t sclklow 151.5 ns din to sclk setup t dinsetup 30 ns din to sclk hold t dinhold 10 ns ncs fall to sclk setup t ncssetup 30 ns sclk fall to dout & sstrb hold t outhold c load = 20pf 10 ns sclk fall to dout & sstrb valid t outvalid c load = 20pf 40 ns ncs rise to dout & sstrb disable t outdisable c load = 20pf 10 60 ns ncs fall to dout & sstrb enable t outenable c load = 20pf 60 ns ncs pulse width high t ncshigh 100 ns table 8: timing characterisitics (vdd = +2.7v to + 5.25v; ? op = ? opmin ? ? opmax ) figure 15 detailed timing diagram ncs sclk din sstrb dout t t sclkhigh scl t sclklow t dinhold t dinsetup t ncssetup t outvalid t outenable t outenable t outdisable t outhold t ncshig
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 22 of 26 outpu t code format zadcs10x2 family devices do all support unipolar and bi polar operation modes. the digital output code is straight binary in unipolar mode. it ranges from 0x00 for an input voltage difference of 0v to 0xff for an input voltage difference of vref (full scale = fs). the first code transition (0x00 ? 0x01) occurs at a voltage equivalent to ? lsb, the last (0xfe ? 0xff) at vref-1.5 lsb. see also figure 16 for details. in bipolar mode a two?s complement coding is applied. code transitions occur again halfway between successive integer lsb values. the transfer function is shown in figure 17 . figure 16 : unipolar transfer function figure 17: bipolar transfer function 2.5. power dissipation the zadcs1 0x2 family offers three different ways to save operating current between conversions. two different software controlled power down modes can be ac tivated to automatically shut-down the device after completion of a conversion. they differ in t he amount of circuitry that is powered down. software power down full power down mode shuts down the entire analog part of the ic, reducing the static idd of the device to less than 0.5a if no external clock is provided at sclk. fast power down mode is only useful with zadcs10x2v devices if the internal voltage reference is used. during fast power-down the bandgap and the vrefadj output buffer are kept alive while all other inte rnal analog circuitry is shut down. the benefit of fast power down mode is a shorter turn on time of the reference compared to full power-down mode. this is basically due to the fact that the low pass which is formed at the vrefadj output by the internal 20k ? resistor and the external buffer capacitor of 47nf is not discharged in fast power-down mode. the settling time of the low pass at vrefadj is about 7ms to re ach 10 bit accuracy. the fast power down mode omits this settling and reduces the turn on time to about 200s. to wake up the ic out of either software power down mode, it is sufficient to send a start bit while ncs is low. since micro controllers can commonly transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device. in all application cases where an external reference voltage is supplied (basic zadcs10x2 and zadcs10x2 v with vrefadj tied to vdd) there is no turn on time to be considered. the first conversion is already valid. fast power-down and full power-down mode do not show any difference in this configuration. 11 ? 111 11 ? 110 11 ? 101 00 ? 000 00 ? 001 00 ? 010 1 2 3 fs 0 in p ut volta g e ( lsb ) fs-3/2 lsb zs = v ( in- ) fs = v ref +v(in- ) 1lsb = v ref 1024 (zs) out p ut code out p ut code zs = v ( in- ) + fs = ?v +v(in-) ref 01 ? 111 01 ? 110 10 ? 000 10 ? 001 00 ? 000 +fs -fs in p ut volta g e ( lsb ) +fs-3/2 lsb 1lsb = v ref 1024 00 ? 001 00 ? 011 11 ? 111 11 ? 110 - fs = -?v +v(in-) ref 11 ? 101 zs
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 23 of 26 hardware power down the third power down mode is called hardware power-down. it is initiated by pulling the nshdn pin low. if this condition is true, the device w ill immediately shut down all circuitry just as in full power down-mode. the ic wakes up if nshdn is tied high. there is no internal pull-up that would allow nshdn to float during normal operation. this ensures the lowest pos sible power consumption in power down mode. general power considerations even without activating any power down mode, the devic es out of the zadcs10x2 fa mily reduce their power consumption between conversions automatically. the com parator, which contributes a considerable amount to the overall current consumption of the device, is sh ut off as soon as a conversion is ended. it gets turned on at the start of the next acquisition period. this expl ains the difference between the iddstatic and iddactive measurements shown in chapter 1.6 typical operating characteristics . the avera ge current consumption of the device depe nds very much on the sampling frequency and the type of protocol used to communicate with the device. in order to achieve the lowest powe r consumption at low sampling frequencies, it is suggested to keep the conversion clock frequency at the maximum level of 3.3mhz and to power down the device between consecutive conversions. figure 18 shows the characteristic current consumption of the zadcs10x2 family with external reference su pply versus sampling rate
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 24 of 26 3 layout to achieve o ptimum conversion performance care must be taken in design and layout of the application board. it is highly recommended to use printed circuit boar ds instead of wire wrap designs and to establish a single point star connection ground system towards agnd (see figure 19 ). for optim al noise performance the star point should be lo cated very close to the agnd pin of the converter. the ground return to the power supply should be as short as possible and low impedance. all other analog ground points of external circuitry that is related to the a/d converter as well as the dgnd pin of the device should be connected to this ground poin t too. any other digital ground system should be kept apart as far as possible and connect on the power supply point only. analog and digital signal domains should also be separ ated as well as possible and analog input signals should be shielded by agnd ground planes from electromagnetic interferences. four-layer pcb boards that allow smaller vertical distances between the ground plane and the shielded signals do generally show a better performance than two-layer boards. the sampling phase is the most critical portion of the ov erall conversion timing for signal distortion. if possible, the switching of any high power devic es or nearby digital logic should be avoided during the sampling phase of the converter. current consumption vs. sample rate external clock mode, external v ref , f sclk = 3.3mhz 1 10 100 1000 10000 1 10 100 1000 sample rate (ksps) average supply current (a) figure 18: supply current versus sampling rate figure 19: optimal power-supply grounding system optional r = 10 ? vdd1 (+2.7 ? +5.25v) zadcs10x2 family power supplies com dgnd other dgnd gnd digital dvdd circuitr y vdd2 the fully differential internal architecture of the za dcs10x2 family ensures very good suppression of power supply noise. nevertheless, the sar architecture is generally sensitive to glitches or sudden changes of the power supply that occur shortly befor e the latching of the comparator outpu t. it is therefore recommended to bypass the power supply connection very close to the device with capacitors of 0.1f (ceramic) and >1f (electrolytic). in case of a noisy supply, an additional se ries resistor of 5 to 10 ohms can be used to low-pass filter the supply voltage. the reference voltage should alwa ys be bypassed with capacitors of 0.1f (ceramic) and 4.7f (electrolytic) as close as possible to the vref pin. if v ref is provided by an external source, any series resistance in the v ref supply path can cause a gain error of the converter. duri ng conversion, a dc current of about 100a is drawn through the vref pin that could cause a noticeable voltage drop across the resistance.
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 25 of 26 4 package drawing zadcs1 082 devices are delivered in a 20-pin ssop- package that has the dimensions as shown in figure 20 and table 9 . zadcs1042 and zadcs1022 devices apply respective 16-pin and 14-pin ssop-packages. their dim ensions are specified in table 9 and table 10 . figure 20: package outline dimensions symbol a a 1 a 2 b p c d e e nom h e l p z k ? nominal 1.86 0.13 1.73 0.30 0. 15 7.20 5.30 7.80 4 maximum 1.99 0.21 1.78 0.38 0. 20 7.33 5.38 7.90 0.74 8 minimum 1.73 0.05 1.68 0.25 0.09 7.07 5.20 0.65 7.65 0.63 0.25 0 table 9: package dimensions for zadc1082 devices (mm) symbol a a 1 a 2 b p c d e e nom h e l p z k ? nominal 1.86 0.13 1.73 0.30 0. 15 6.20 5.30 7.80 4 maximum 1.99 0.21 1.78 0.38 0. 20 6.07 5.38 7.90 0.89 10 minimum 1.73 0.05 1.68 0.25 0.09 6.33 5.20 0.65 7.65 0.63 0.25 0 table 10: package dimensions for zadc1042 devices (mm) symbol a a 1 a 2 b p c d e e nom h e l p z k ? nominal 1.86 0.13 1.73 0.30 0. 15 6.20 5.30 7.80 4 maximum 1.99 0.21 1.78 0.38 0. 20 6.33 5.38 7.90 1.22 10 minimum 1.73 0.05 1.68 0.25 0.09 6.07 5.20 0.65 7.65 0.63 0.25 0 table 11: package dimensions for zadc1022 devices (mm)
zadcs1082/1042/1022 10-bit, 250ksps, adc family data sheet october 12, 2011 ? 2011 zentrum mikroelektronik dresden ag ? rev. 2.0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 26 of 26 sales and further information www.zmdi.com adc@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 8413 excelsior drive suite 200 madison, wi 53717 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan phone +49 (0)351.8822.7232 fax +49 (0)351.8822.87232 phone +1 (608) 829-1987 fax +1 (631) 549-2882 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886 2 2377 8189 fax +886 2 2377 8199 disclaimer : this information applies to a product under development. its characteristics and specifications are preliminary and subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. t he information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for an y special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (includi ng negligence), strict liability, or otherwise.
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: zmdi: ? zadcs1022is14t? ZADCS1022VIS14T? zadcs1042is16t? zadcs1042vis16t? zadcs1082is20t? zadcs1082vis20t

▲Up To Search▲

Price & Availability of ZADCS1022VIS14T

	To Download ZADCS1022VIS14T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .